1. Field of the Invention
The present invention relates to a driver circuit, and more particularly, to a driver circuit of a display device.
2. Description of the Related Art
Techniques of manufacturing a semiconductor device, for example, a thin film transistor (TFT), which has a semiconductor thin film formed on an inexpensive glass substrate, have been making rapid progress in recent years. This is because there is an increasing demand for active matrix liquid crystal display devices (liquid crystal display devices).
In the active matrix liquid crystal display device, several hundred thousands to several millions of TFTs are arranged in matrix in a pixel portion, and electric charges going into and out of pixel electrodes that are connected to each TFT are controlled by the switching function of the TFTs.
Conventionally, thin film transistors employing an amorphous silicon film formed on a glass substrate are arranged in the pixel portion.
Further, in recent years, a structure is known in which quartz is utilized as a substrate and thin film transistors are manufactured from a polycrystalline silicon film. In this case, both a peripheral driver circuit and a pixel portion are constructed of the thin film transistors formed on the quartz substrate.
Still further, recently, also known is a technique in which thin film transistors using a crystalline silicon film are formed on a glass substrate by laser annealing or other techniques. Employment of this technique allows a pixel portion and a peripheral driver circuit to be integrated on the glass substrate.
Active matrix liquid crystal display devices are mainly used in notebook personal computers. Different from analog data used in the current television signals (NTSC or PAL) or the like, the personal computer outputs digital data to a display device. Conventionally, digital data from a personal computer are converted into analog data and then inputted into the active matrix liquid crystal display device, or to an active matrix liquid crystal display device that utilizes an externally attached digital driver.
Therefore, a liquid crystal display device having a digital interface capable of directly inputting digital data from outside is in the spotlight.
Here, a portion of a source driver of the liquid crystal display device having a digital interface that is recently in the spotlight is shown in FIG. 17. In FIG. 17, reference numeral 8000 denotes a shift register circuit and reference numeral 8100 denotes a digital data latch circuit. The shift register 8000 generates a timing signal on the basis of a clock signal (CLK), a clock back signal (CLKB), and a start pulse (SP) which are supplied from outside, and then sends out the above timing signal to the digital data latch circuit 8100. Based on the timing signal from the shift register circuit 8000, the digital data latch circuit 8100 samples (takes in) and stores and holds digital data inputted from outside.
Note that a scanning direction switching circuit is included in the shift register circuit 8000 shown in FIG. 17. The scanning direction switching circuit is a circuit for controlling the order of the output of the timing signal from the shift register circuit 8000 from left to right or from right to left in accordance with a scanning direction switching signal inputted from outside.
In a conventional shift register circuit such as the shift register circuit 8000 shown in FIG. 17, the shift register circuit 8000 is complicated and constructed by a large number of elements. In the present situation in which an active matrix liquid crystal display device with higher resolution is demanded, the surface area of the shift register circuit becomes larger as its resolution is improved. Thus, the number of elements constructing the shift register circuit is also increased.
Because of this increase in the number of elements, the production yield in the entire liquid crystal display devices becomes worse. Further, if the possessed surface area of the circuits becomes larger, it hinders the making of small scale liquid crystal display devices.
Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is therefore to attain improvement in production yield and compactness of the active matrix liquid crystal display device by providing a driver circuit that is simple as well as possessing a small surface area.
FIG. 1 is referenced. A driver circuit of the present invention is shown in FIG. 1. Reference numeral 100 denotes a shift register circuit and reference numeral 200 denotes a group of digital data latch circuits. Note that only 5 stages of the shift register circuit 100 and 1 bit of the group of digital data latch circuit 200 corresponding to the 5 stages of the shift register circuit 100 are shown in FIG. 1 for explanation conveniences. However, the driver circuit of the present invention may have n stages of shift register circuits, and may also have m bits of the group of digital data latch circuits.
The shift register circuit 100 has a plurality of register circuits 110, 120, 130, 140, and 150. An explanation is given here taking the register circuit 110 as an example. The register circuit 110 has a clocked inverter circuit 111 and an inverter circuit 112. In addition thereto, the register circuit 110 has a signal line 113 and the parasitic capacitance of the signal line 113 may be considered as elements constructing the register circuit. Further, a clock signal (CLK), a clock back signal (CLKB), and a start pulse (SP) from outside are inputted to the shift register circuit 100. These signals are fed to the register circuits 110, 120, 130, 140, and 150.
The clocked inverter circuit 111 operates in the same period with the inputted clock signal (CLK) and the clock back signal (CLKB) to thereby output the inputted start pulse (SP) to the inverter circuit 112. The inverter circuit 112 then outputs the inputted pulse signal to the signal line 113 and the register circuit 120 of the next stage. However, since a large number of elements are connected to the signal line 113, its parasitic capacitance is large resulting in having a high load. The present invention actively utilizes this high load due to the large parasitic capacitance of the signal line 113. Accordingly, timing signals are sequentially outputted at constant intervals from the register circuits 110, 120, 130, 140, and 150.
The group of digital data latch circuits 200 has digital data latch circuits 210, 220, 230, 240, and 250. An explanation is given taking the digital data latch circuit 210 as an example. The digital data latch circuit 210 has a first N-channel transistor 211, a second N-channel transistor 212, a P-channel transistor 213, and inverter circuits 214 and 215. Digital data and a reset signal (Res) are inputted to the digital data latch circuit 210 from outside. Further, a source or drain of the P-channel transistor 213 is connected to a first power source voltage (VDD_1). The first power source voltage (VDD_1) is set higher than the operation electric potential of the N-channel transistor.
Immediately before the start pulse (SP) is fed to the shift register circuit 100, the reset signal (Res) is inputted to thereby feed the first power source voltage (VDD_1) to inverter circuits 214, 224, 234, 244, and 254. In other words, a positive logic xe2x80x9c1 (Hi)xe2x80x9d signal is inputted.
The timing signal from the register circuit 110 outputted through the signal line 113 is inputted to the N-channel transistor 212 of the digital data latch circuit 210, whereby the N-channel transistor 212 starts to operate. In addition, when a timing signal from the next stage register circuit 120 outputted through the signal line 123 is inputted to the N-channel transistor 211 of the digital data latch circuit 210 and the N-channel transistor 211 starts to operate, then digital data inputted from outside is taken in by the inverter circuit 214 where the digital data is held by the inverter circuits 214 and 215. At this point, if the inputted digital data from outside is xe2x80x9c1 (Hi)xe2x80x9d, a digital data xe2x80x9c1xe2x80x9d is held by the inverter circuits 214 and 215. On the other hand, if the inputted digital data from outside is xe2x80x9c0 (Lo)xe2x80x9d, xe2x80x9c0xe2x80x9d is inputted to the inverter circuit 214, whereby the digital data xe2x80x9c0 (Lo)xe2x80x9d is held by the inverter circuits 214 and 215.
FIG. 19 is referenced next. The driver circuit of the present invention is shown in FIG. 19. Reference numeral 3800 denotes a shift register circuit and reference numeral 3900 denotes a group of digital data latch circuits. Note that only 5 stages of the shift register circuit 3800 and 1 bit of the group of digital data latch circuit 3900 corresponding to the 5 stages of the shift register circuit 3800 are shown in FIG. 19 for explanation conveniences. However, the driver circuit of the present invention may have n stages of shift register circuits, and may also have m bits of the group of digital data latch circuits.
The driver circuit of the present invention that will be described here is structured differently from the driver circuit and the group of digital data latch circuits of the present invention illustrated in FIG. 1.
The group of digital data latch circuits 3900 has digital data latch circuits 3910, 3920, 3930, 3940, and 3950. An explanation is given here taking the digital data latch circuit 3910 as an example. The digital data latch circuit 3910 has a first P-channel transistor 3911, a second P-channel transistor 3912, an N-channel transistor 3913, and inverter circuits 3914 and 3915. Digital data and a reset signal (Res) are inputted to the digital data latch circuit 3910 from outside. Further, a source or drain of the N-channel transistor 3913 is connected to a second power source voltage (VSS_1). The second power source voltage (VSS_1) is set lower than the operating electric potential of the P-channel transistor.
Immediately before the start pulse (SP) is fed to the shift register circuit 3800, the reset signal (Res) is inputted to thereby feed the second power source voltage (VSS_1) to inverter circuits 3914, 3924, 3934, 3944, and 3954. In other words, a negative logic xe2x80x9c0 (Lo)xe2x80x9d signal is inputted.
A timing signal from a register circuit 3810 outputted through a signal line 3813 is inputted to the P-channel transistor 3912 of the digital data latch circuit 3910, whereby the P-channel transistor 3812 starts to operate. In addition, when a timing signal from a next stage register circuit 3820 outputted through a signal line 3823 is inputted to the P-channel transistor 3911 of the digital data latch circuit 3910 and the P-channel transistor 3911 starts to operate, then digital data inputted from outside is taken in by the inverter circuit 3914 where the digital data is held by the inverter circuits 3914 and 3915. At this point, if the inputted digital data from outside is xe2x80x9c0 (Lo)xe2x80x9d, a digital data xe2x80x9c0xe2x80x9d is held by the inverter circuits 3914 and 3915. On the other hand, if the inputted digital data from outside is xe2x80x9c1 (Hi)xe2x80x9d, xe2x80x9c1xe2x80x9d is inputted to the inverter circuit 3914, whereby the digital data xe2x80x9c1 (Hi)xe2x80x9d is held by the inverter circuits 3914 and 3915.
It should be noted that all the register circuits and all the digital data latch circuits perform the above explained operations.
The number of elements constructing the driver circuit of the present invention can be half or less than the number of elements of the conventional driver circuit by adopting the above structure.
Here, the structure of the present invention will be described below.
A driver circuit according to a first aspect of the present invention is comprised of:
a shift register circuit having a plurality of register circuits including a clocked inverter circuit and an inverter circuit connected in series;
a plurality of digital data latch circuits having a first N-channel transistor and a second N-channel transistor in which the sources or drains are connected in series, a P-channel transistor, and
a digital data holding circuit, and is characterized in that:
the clocked inverter circuit and the inverter circuit generate a timing signal on the basis of a clock signal, a clock back signal, and a start pulse inputted from outside, and feeds the timing signal to a register circuit neighboring the register circuit and a gate electrode of the second N-channel transistor;
the P-channel transistor inputs a first electric current voltage to the digital data holding circuit in accordance with a reset signal that is inputted from outside to a gate electrode of the P-channel transistor;
the first N-channel transistor takes in digital data inputted on the basis of the timing signal and feeds the digital data to the source or the drain of the second N-channel transistor; and
the timing signal outputted from a register circuit neighboring the register circuit is fed to a gate electrode of the first N-channel transistor.
A driver circuit according to a second aspect of the present invention is comprised of:
a shift register circuit having a register circuit including a clocked inverter circuit and an inverter circuit connected in series;
a digital data latch circuit having a first N-channel transistor and a second N-channel transistor in which the sources or drains are connected in series, a P-channel transistor, and
a digital data holding circuit, and is characterized in that:
a gate electrode of the second N-channel transistor is connected to the output line of the register circuit, a source or a drain of the second N-channel transistor is connected to a source or a drain of the first N-channel transistor, and the other end of the source or the drain of the second N-channel transistor is connected to the digital data holding circuit;
a gate electrode of the first N-channel transistor is connected to the output line of a register circuit neighboring the register circuit and the other end of the source or the drain of the first N-channel transistor is connected to a signal line to which digital data are inputted; and
a gate electrode of the P-channel transistor is connected to a signal line to which a reset signal is inputted and one end of a source or a drain of the P-channel transistor is connected to a first power source whereas the other end of the source or the drain of the P-channel transistor is connected to the digital data holding circuit.
A driver circuit according to a third aspect of the present invention is comprised of:
a shift register circuit having a plurality of register circuits including a clocked inverter circuit and an inverter circuit connected in series;
a plurality of digital data latch circuits having a first P-channel transistor and a second P-channel transistor in which the sources or drains are connected in series, an N-channel transistor, and
a digital data holding circuit, and is characterized in that:
the clocked inverter circuit and the inverter circuit generate a timing signal on the basis of a clock signal, a clock back signal, and a start pulse inputted from outside and feeds the timing signal to a register circuit neighboring the register circuit and to a gate electrode of the second P-channel transistor;
the N-channel transistor feeds a second electric current voltage to the digital data holding circuit in accordance with a reset signal that is inputted from outside to a gate electrode of the N-channel transistor;
the first P-channel transistor takes in digital data inputted on the basis of the timing signal and feeds the digital data to the source or the drain of the second P-channel transistor; and
the timing signal outputted from a register circuit neighboring the register circuit is fed to a gate electrode of the first P-channel transistor.
A driver circuit according to a fourth aspect of the present invention is comprised of:
a shift register circuit having a register circuit including a clocked inverter circuit and an inverter circuit connected in series;
a digital data latch circuit having a first P-channel transistor and a second P-channel transistor in which the sources or drains are connected in series, an N-channel transistor, and
a digital data holding circuit, and is characterized in that:
a gate electrode of the second P-channel transistor is connected to the output line of the register circuit, a source or a drain of the second P-channel transistor is connected to a source or a drain of the first P-channel transistor, and the other end of the source or the drain of the second P-channel transistor is connected to the digital data holding circuit;
a gate electrode of the first P-channel transistor is connected to the output line of a register circuit neighboring the register circuit and the other end of the source or the drain of the first P-channel transistor is connected to a signal line to which digital data are inputted; and
a gate electrode of the N-channel transistor is connected to a signal line to which a reset signal is inputted and one end of a source or a drain of the N-channel transistor is connected to a second power source whereas the other end of the source or the drain of the N-channel transistor is connected to the digital data holding circuit.